- Should be experienced chip integration and have lead integration of high complexity SOCs.
- Experiencing using clear case is a must.
- Experienced with VHDL/Verilog/modelsim/Spyglass/FV/CDC and familiarity with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable.
- Will be responsible in coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables.
- Tools used Modelsim/VCS/VERdi/Spyglass/Clear case. /Mentor Zero-in. Responsible for Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action. In ECO phase, will coordinate all the ECOs. RTL and netlist releases. ENG-III/IV
Education: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics