Job Description:

• Responsible for IP or Subsystem or full-chip level verification.
• For IP verification, responsibility will be end-to-end. Scripting languages Perl, Python.
• Expertise in Verilog and HVL like System VerilogGLS, Power Aware (PA), Analog-Mixed signal (AMS)) simulations.
• Assertions Expertise in verification methodologies like UVM/OVM based CDV (constraint driven verification)/MDV (metric driven verification).
  Experience working with geographically distributed teams.
• Experience in verification at both module level and chip level Protocols worked on USB, I2S, SPDIF.
• Expertise in programming language C/C++ Good verbal and written communication skills.

Responsibilities will include one or more of the following:

• Understanding spec, interact w/ designers/architect to get queries clarified
• Development of vPlans, ensure complete mapping to requirements
• Document test bench architecture
• Test bench Development
• Execute tests and coverage closure
• Work w/ designers to close on open issues
• Generate test/coverage reports
• Prepare weekly status report

Education: B.E/B.Tech or M.E/M.Tech/M.S  in Electrical or Electronics