- Should be involved in the design and development of High speed interface circuits upto 10gbps, pci Gen3,2,1 USB 3.0, MIPI IOs & LVDS.
- Should be responsible for circuit design of ADC’s, DAC’s, PLL’s, Filter, adaptive equalizers, finite-impulse response (FIR) filter, decision-feedback equalizer (DFE), Serdes, clock and data recovery (CDR) circuits and other timing circuits.
- Should have working knowledge in the technology nodes of 65, 45/40, 28nm is preferred.
- Responsible for the design and implementation of the blocks related to SerDes.
- Hands on tool expertise with tools such as cadence schematic design, simulation tools, exposure to scripting techniques.
Education: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics